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<a href="#pub-attribs">Data Fields</a>  </div>
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<div class="title">cy_stc_dma_descriptor_config_t Struct Reference<div class="ingroups"><a class="el" href="group__group__dma.html">DMA          (Direct Memory Access)</a> &raquo; <a class="el" href="group__group__dma__data__structures.html">Data Structures</a></div></div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>This structure is a configuration structure pre-initialized by the user and passed as a parameter to the <a class="el" href="group__group__dma__descriptor__functions.html#gab1610fab6f2dd5fd25c031ac0aa9d8cb">Cy_DMA_Descriptor_Init()</a>. </p>
<p>It can be allocated in RAM/flash (the user's choice). In case of flash allocation, there is a possibility to reinitialize the descriptor in runtime. This structure has all the parameters of the descriptor as separate parameters. Most of these parameters are represented in the <a class="el" href="structcy__stc__dma__descriptor__t.html">cy_stc_dma_descriptor_t</a> structure as bitfields. </p>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:afcc039279bc1e7d50b0813778772f3c0"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__dma__enums.html#ga8ea649c82d5e7d4d4bd72403468aadee">cy_en_dma_retrigger_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#afcc039279bc1e7d50b0813778772f3c0">retrigger</a></td></tr>
<tr class="memdesc:afcc039279bc1e7d50b0813778772f3c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specifies whether the DW controller should wait for the input trigger to be deactivated.  <a href="#afcc039279bc1e7d50b0813778772f3c0">More...</a><br /></td></tr>
<tr class="separator:afcc039279bc1e7d50b0813778772f3c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a24d1190242541ecaacf98b3f88fbb76f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__dma__enums.html#ga46664f020f211baf0651e6c85c3c3e76">cy_en_dma_trigger_type_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#a24d1190242541ecaacf98b3f88fbb76f">interruptType</a></td></tr>
<tr class="memdesc:a24d1190242541ecaacf98b3f88fbb76f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the event that triggers an interrupt.  <a href="#a24d1190242541ecaacf98b3f88fbb76f">More...</a><br /></td></tr>
<tr class="separator:a24d1190242541ecaacf98b3f88fbb76f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a52d032ede5148bd7ccd876a889a75b6e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__dma__enums.html#ga46664f020f211baf0651e6c85c3c3e76">cy_en_dma_trigger_type_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#a52d032ede5148bd7ccd876a889a75b6e">triggerOutType</a></td></tr>
<tr class="memdesc:a52d032ede5148bd7ccd876a889a75b6e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the event that triggers an output.  <a href="#a52d032ede5148bd7ccd876a889a75b6e">More...</a><br /></td></tr>
<tr class="separator:a52d032ede5148bd7ccd876a889a75b6e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5022f09baba084b5a4d970e6c6c17fc8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__dma__enums.html#ga75740ce8bf02f62bc9e6c86307369f67">cy_en_dma_channel_state_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#a5022f09baba084b5a4d970e6c6c17fc8">channelState</a></td></tr>
<tr class="memdesc:a5022f09baba084b5a4d970e6c6c17fc8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specifies whether the channel is enabled or disabled on completion of descriptor.  <a href="#a5022f09baba084b5a4d970e6c6c17fc8">More...</a><br /></td></tr>
<tr class="separator:a5022f09baba084b5a4d970e6c6c17fc8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a812ec882fb732307e9fd783f56424b4c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__dma__enums.html#ga46664f020f211baf0651e6c85c3c3e76">cy_en_dma_trigger_type_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#a812ec882fb732307e9fd783f56424b4c">triggerInType</a></td></tr>
<tr class="memdesc:a812ec882fb732307e9fd783f56424b4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets what type of transfer is triggered.  <a href="#a812ec882fb732307e9fd783f56424b4c">More...</a><br /></td></tr>
<tr class="separator:a812ec882fb732307e9fd783f56424b4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab91e69de7bf26cba25353fe627e5faf2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__dma__enums.html#ga167a5222a0d666c6ce9e8382e56ac192">cy_en_dma_data_size_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#ab91e69de7bf26cba25353fe627e5faf2">dataSize</a></td></tr>
<tr class="memdesc:ab91e69de7bf26cba25353fe627e5faf2"><td class="mdescLeft">&#160;</td><td class="mdescRight">The size of the data bus for transfer.  <a href="#ab91e69de7bf26cba25353fe627e5faf2">More...</a><br /></td></tr>
<tr class="separator:ab91e69de7bf26cba25353fe627e5faf2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa79133a1c99f1802ced9e31a4970f623"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__dma__enums.html#ga2e6a1fad6945ca581ebd0fdbb8748314">cy_en_dma_transfer_size_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#aa79133a1c99f1802ced9e31a4970f623">srcTransferSize</a></td></tr>
<tr class="memdesc:aa79133a1c99f1802ced9e31a4970f623"><td class="mdescLeft">&#160;</td><td class="mdescRight">The source transfer size.  <a href="#aa79133a1c99f1802ced9e31a4970f623">More...</a><br /></td></tr>
<tr class="separator:aa79133a1c99f1802ced9e31a4970f623"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af060eb3020cb431eb42065b93350285b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__dma__enums.html#ga2e6a1fad6945ca581ebd0fdbb8748314">cy_en_dma_transfer_size_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#af060eb3020cb431eb42065b93350285b">dstTransferSize</a></td></tr>
<tr class="memdesc:af060eb3020cb431eb42065b93350285b"><td class="mdescLeft">&#160;</td><td class="mdescRight">The destination transfer size.  <a href="#af060eb3020cb431eb42065b93350285b">More...</a><br /></td></tr>
<tr class="separator:af060eb3020cb431eb42065b93350285b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afaadf17e4d711b1d357787ff17756f8e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__dma__enums.html#ga69516534f5a562e8a2f55bb4203851d0">cy_en_dma_descriptor_type_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#afaadf17e4d711b1d357787ff17756f8e">descriptorType</a></td></tr>
<tr class="memdesc:afaadf17e4d711b1d357787ff17756f8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">The type of the descriptor.  <a href="#afaadf17e4d711b1d357787ff17756f8e">More...</a><br /></td></tr>
<tr class="separator:afaadf17e4d711b1d357787ff17756f8e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2d445d72c32caec445defca4ef8898cf"><td class="memItemLeft" align="right" valign="top">void *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#a2d445d72c32caec445defca4ef8898cf">srcAddress</a></td></tr>
<tr class="memdesc:a2d445d72c32caec445defca4ef8898cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">The source address of the transfer.  <a href="#a2d445d72c32caec445defca4ef8898cf">More...</a><br /></td></tr>
<tr class="separator:a2d445d72c32caec445defca4ef8898cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a02bb836b663f7bdf8979e806dc813917"><td class="memItemLeft" align="right" valign="top">void *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#a02bb836b663f7bdf8979e806dc813917">dstAddress</a></td></tr>
<tr class="memdesc:a02bb836b663f7bdf8979e806dc813917"><td class="mdescLeft">&#160;</td><td class="mdescRight">The destination address of the transfer.  <a href="#a02bb836b663f7bdf8979e806dc813917">More...</a><br /></td></tr>
<tr class="separator:a02bb836b663f7bdf8979e806dc813917"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af487efdef7f9cd209f783d24ce1a4bd9"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#af487efdef7f9cd209f783d24ce1a4bd9">srcXincrement</a></td></tr>
<tr class="memdesc:af487efdef7f9cd209f783d24ce1a4bd9"><td class="mdescLeft">&#160;</td><td class="mdescRight">The address increment of the source after each X-loop transfer.  <a href="#af487efdef7f9cd209f783d24ce1a4bd9">More...</a><br /></td></tr>
<tr class="separator:af487efdef7f9cd209f783d24ce1a4bd9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a389c0565be605fcda996e76eb9552853"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#a389c0565be605fcda996e76eb9552853">dstXincrement</a></td></tr>
<tr class="memdesc:a389c0565be605fcda996e76eb9552853"><td class="mdescLeft">&#160;</td><td class="mdescRight">The address increment of the destination after each X-loop transfer.  <a href="#a389c0565be605fcda996e76eb9552853">More...</a><br /></td></tr>
<tr class="separator:a389c0565be605fcda996e76eb9552853"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a23df6ae648618339b9221ad95363f328"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#a23df6ae648618339b9221ad95363f328">xCount</a></td></tr>
<tr class="memdesc:a23df6ae648618339b9221ad95363f328"><td class="mdescLeft">&#160;</td><td class="mdescRight">The number of transfers in an X-loop.  <a href="#a23df6ae648618339b9221ad95363f328">More...</a><br /></td></tr>
<tr class="separator:a23df6ae648618339b9221ad95363f328"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a74d85b6aacd82758cfa183f20787fb50"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#a74d85b6aacd82758cfa183f20787fb50">srcYincrement</a></td></tr>
<tr class="memdesc:a74d85b6aacd82758cfa183f20787fb50"><td class="mdescLeft">&#160;</td><td class="mdescRight">The address increment of the source after each Y-loop transfer.  <a href="#a74d85b6aacd82758cfa183f20787fb50">More...</a><br /></td></tr>
<tr class="separator:a74d85b6aacd82758cfa183f20787fb50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afb2f61e8c6c07c5dde46b9a3407f526b"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#afb2f61e8c6c07c5dde46b9a3407f526b">dstYincrement</a></td></tr>
<tr class="memdesc:afb2f61e8c6c07c5dde46b9a3407f526b"><td class="mdescLeft">&#160;</td><td class="mdescRight">The address increment of the destination after each Y-loop transfer.  <a href="#afb2f61e8c6c07c5dde46b9a3407f526b">More...</a><br /></td></tr>
<tr class="separator:afb2f61e8c6c07c5dde46b9a3407f526b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4708f3e8e216ff8a637cf9caf6084f23"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#a4708f3e8e216ff8a637cf9caf6084f23">yCount</a></td></tr>
<tr class="memdesc:a4708f3e8e216ff8a637cf9caf6084f23"><td class="mdescLeft">&#160;</td><td class="mdescRight">The number of X-loops in the Y-loop.  <a href="#a4708f3e8e216ff8a637cf9caf6084f23">More...</a><br /></td></tr>
<tr class="separator:a4708f3e8e216ff8a637cf9caf6084f23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6bbdfa16f3b38866a9e6d4242814b45e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structcy__stc__dma__descriptor__t.html">cy_stc_dma_descriptor_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dma__descriptor__config__t.html#a6bbdfa16f3b38866a9e6d4242814b45e">nextDescriptor</a></td></tr>
<tr class="memdesc:a6bbdfa16f3b38866a9e6d4242814b45e"><td class="mdescLeft">&#160;</td><td class="mdescRight">The next descriptor to chain after completion.  <a href="#a6bbdfa16f3b38866a9e6d4242814b45e">More...</a><br /></td></tr>
<tr class="separator:a6bbdfa16f3b38866a9e6d4242814b45e"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Field Documentation</h2>
<a id="afcc039279bc1e7d50b0813778772f3c0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#afcc039279bc1e7d50b0813778772f3c0">&#9670;&nbsp;</a></span>retrigger</h2>

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          <td class="memname"><a class="el" href="group__group__dma__enums.html#ga8ea649c82d5e7d4d4bd72403468aadee">cy_en_dma_retrigger_t</a> cy_stc_dma_descriptor_config_t::retrigger</td>
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<p>Specifies whether the DW controller should wait for the input trigger to be deactivated. </p>

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<a id="a24d1190242541ecaacf98b3f88fbb76f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a24d1190242541ecaacf98b3f88fbb76f">&#9670;&nbsp;</a></span>interruptType</h2>

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          <td class="memname"><a class="el" href="group__group__dma__enums.html#ga46664f020f211baf0651e6c85c3c3e76">cy_en_dma_trigger_type_t</a> cy_stc_dma_descriptor_config_t::interruptType</td>
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<p>Sets the event that triggers an interrupt. </p>
<p>See <a class="el" href="group__group__dma__enums.html#ga46664f020f211baf0651e6c85c3c3e76">cy_en_dma_trigger_type_t</a>. </p>

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<a id="a52d032ede5148bd7ccd876a889a75b6e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a52d032ede5148bd7ccd876a889a75b6e">&#9670;&nbsp;</a></span>triggerOutType</h2>

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          <td class="memname"><a class="el" href="group__group__dma__enums.html#ga46664f020f211baf0651e6c85c3c3e76">cy_en_dma_trigger_type_t</a> cy_stc_dma_descriptor_config_t::triggerOutType</td>
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<p>Sets the event that triggers an output. </p>
<p>See <a class="el" href="group__group__dma__enums.html#ga46664f020f211baf0651e6c85c3c3e76">cy_en_dma_trigger_type_t</a>. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a5022f09baba084b5a4d970e6c6c17fc8">&#9670;&nbsp;</a></span>channelState</h2>

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<p>Specifies whether the channel is enabled or disabled on completion of descriptor. </p>
<p>See <a class="el" href="group__group__dma__enums.html#ga75740ce8bf02f62bc9e6c86307369f67">cy_en_dma_channel_state_t</a>. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a812ec882fb732307e9fd783f56424b4c">&#9670;&nbsp;</a></span>triggerInType</h2>

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<p>Sets what type of transfer is triggered. </p>
<p>See <a class="el" href="group__group__dma__enums.html#ga46664f020f211baf0651e6c85c3c3e76">cy_en_dma_trigger_type_t</a>. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ab91e69de7bf26cba25353fe627e5faf2">&#9670;&nbsp;</a></span>dataSize</h2>

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<p>The size of the data bus for transfer. </p>
<p>See <a class="el" href="group__group__dma__enums.html#ga167a5222a0d666c6ce9e8382e56ac192">cy_en_dma_data_size_t</a>. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aa79133a1c99f1802ced9e31a4970f623">&#9670;&nbsp;</a></span>srcTransferSize</h2>

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<p>The source transfer size. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#af060eb3020cb431eb42065b93350285b">&#9670;&nbsp;</a></span>dstTransferSize</h2>

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<p>The destination transfer size. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#afaadf17e4d711b1d357787ff17756f8e">&#9670;&nbsp;</a></span>descriptorType</h2>

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<p>The type of the descriptor. </p>
<p>See <a class="el" href="group__group__dma__enums.html#ga69516534f5a562e8a2f55bb4203851d0">cy_en_dma_descriptor_type_t</a>. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a2d445d72c32caec445defca4ef8898cf">&#9670;&nbsp;</a></span>srcAddress</h2>

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<p>The source address of the transfer. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a02bb836b663f7bdf8979e806dc813917">&#9670;&nbsp;</a></span>dstAddress</h2>

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<p>The destination address of the transfer. </p>
<p>For CPUSS_ver2 only: for CRC transfer, the CRC result without post-processing (reversing and/or XORing, if used) is placed into the dstAddress. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#af487efdef7f9cd209f783d24ce1a4bd9">&#9670;&nbsp;</a></span>srcXincrement</h2>

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<p>The address increment of the source after each X-loop transfer. </p>
<p>Valid range is -2048 ... 2047. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a389c0565be605fcda996e76eb9552853">&#9670;&nbsp;</a></span>dstXincrement</h2>

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<p>The address increment of the destination after each X-loop transfer. </p>
<p>Valid range is -2048 ... 2047. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a23df6ae648618339b9221ad95363f328">&#9670;&nbsp;</a></span>xCount</h2>

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<p>The number of transfers in an X-loop. </p>
<p>Valid range is 1 ... 256. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a74d85b6aacd82758cfa183f20787fb50">&#9670;&nbsp;</a></span>srcYincrement</h2>

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<p>The address increment of the source after each Y-loop transfer. </p>
<p>Valid range is -2048 ... 2047. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#afb2f61e8c6c07c5dde46b9a3407f526b">&#9670;&nbsp;</a></span>dstYincrement</h2>

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<p>The address increment of the destination after each Y-loop transfer. </p>
<p>Valid range is -2048 ... 2047. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a4708f3e8e216ff8a637cf9caf6084f23">&#9670;&nbsp;</a></span>yCount</h2>

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<p>The number of X-loops in the Y-loop. </p>
<p>Valid range is 1 ... 256. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6bbdfa16f3b38866a9e6d4242814b45e">&#9670;&nbsp;</a></span>nextDescriptor</h2>

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<p>The next descriptor to chain after completion. </p>
<p>A NULL value will signify no chaining. </p>

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